1. Field of the Invention
The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials, and other programmable resistance materials, and to methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, such as chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state. The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
Because the phase change occurs as a result of heating, a relatively large current is needed in order to heat the phase change material and induce the desired phase change. Field effect transistor access devices have been proposed as drivers for phase change memory cells, but field effect transistors (e.g., MOSFET) can have a weaker current drive. Bipolar junction transistors (BJT) can provide larger current drive than field effect transistors, but the integration of bipolar junction transistors with CMOS peripheral circuitry is difficult and results in highly complex designs and manufacturing processes. See, Pellizzer, F., et al., “A 90 nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications,” 2006 Symp. on VLSI Technology Digest of Papers, IEEE 2006.
Diode access devices have been proposed as drivers for phase change memory cells. See, Oh, J. H., et al., “Full Integration of Highly Manufacturable 512 Mb PRAM based on 90 nm Technology,” IEDM 2006, Page(s): 1-4. However, diodes having both regions made of doped polysilicon may have an unacceptably high off current. Diodes having both regions made of doped single-crystal silicon may provide a suitably low off current, but processes for making a diode having both regions made of doped single-crystal silicon are complex. Diode structures have been proposed that include polysilicon for one terminal and single-crystal silicon for another. See, U.S. Pat. No. 7,309,921. However, such structures do not completely solve the problem of high off-current due to the polysilicon terminal, and have not been proposed for memory cell access devices. See, U.S. Pat. No. 7,157,314.
One common technology for interconnecting components on integrated circuits requires the use of buried diffusion lines, which consist of lines of implanted dopants in relatively high concentration, so that they act as conductors in the substrate. A problem that arises with the use of buried diffusion lines or other doped semiconductor features is the formation of parasitic devices. Semiconductor regions that are adjacent the buried diffusion lines can produce carriers during operation. These carriers can migrate into the buried diffusion lines, and activate parasitic devices causing breakdown or current leakage.
Silicides are commonly used in integrated circuit manufacturing to increase the conductivity of doped silicon lines or elements. A common version of the material is referred to as a “salicide”, changing the first two letters of the word to “sa-”, in a reference to self-aligned techniques for forming the material on the chip. A self-aligned process for forming silicide involves depositing a silicide precursor over a substrate that includes exposed regions of silicon, and annealing the silicide precursor to form a silicide in the exposed regions. Then the remaining silicide precursor on the substrate is removed leaving the self-aligned silicide elements. Typical silicide precursors include metals or combinations of metals such as cobalt, titanium, nickel, molybdenum, tungsten, tantalum, and platinum. Also, silicide precursors may include metal nitrides or other metal compounds. Representative uses of silicides in integrated circuit manufacturing are shown in U.S. Pat. Nos. 7,365,385; 7,129,538; 6,815,298; 6,737,675; 6,653,733; 6,649,976 and 6,011,272; and in U.S. Patent Application Publication No. US 2001/0055838.
One limitation on the utilization of silicides arises because there is no practical technique for providing a single crystal silicon node on top of a silicide, or for providing a silicide between two single crystal nodes of silicon, without intervening layers of material. (Compare for example, European Patent Application Publication No. 0 494 598 A1). When forming a silicon element on top of a silicide, only amorphous or polycrystalline silicon have been made in prior art technologies. Thus, certain types of devices, such as diode drivers for memory cells, in which it is preferable to utilize single crystal silicon cannot be formed on top of a silicide contact. This limitation arises in the formation of vertical access devices such as diodes and transistors in memory arrays, and in other vertical device structures.
It is desirable to provide access devices that reliably provide sufficient current for programmable resistance memory cell programming while avoiding problems of cross-talk, that are readily manufacturable at acceptable cost, and that are compatible with high performance logic circuitry.